1. Field of the Invention
The present invention relates to a lithographic technology capable of forming highly precise micro pattern on a substrate in the manufacture of semiconductor integrated circuits, in particular the present invention relates to an intermediate layer composition for multilayer resist process, a pattern-forming method using the same, and laminate.
2. Description of the Related Art
With the rapid progress in the integration degree of semiconductor integrated circuits, requirements for fining of resist pattern and heightening accuracy in lithographic process have increased more and more. To cope with these requirements, technical development for shorter wavelengths of light sources is surely progressing in exposing methods from conventional near ultraviolet rays such as g-rays and i-rays to KrF, ArF and excimer laser beams such as F2, EUV rays and X-rays for higher resolution.
On the other hand, the reduction of accuracy of a resist patterns by the variation in resist film thickness due to the difference in levels of a substrate generated in the manufacture of semiconductor integrated circuits has become an issue. As a result of investigation of uneven substrates, this problem is coming to the easing by the development of CMP technique of flattening. A further serious problem different from this arises. With the tendency of exposure light sources of becoming shorter wavelengths, light absorption of resist materials becomes more and more, so that conventional aromatic ring-based organic polymer materials cannot be used. Further, thinning of resist films is required for the reduction of light absorption and widening of lithographic process window, accordingly sufficient dry etching resistance can be ensured no longer by the conventional monolayer resist process, and there is little likelihood of highly precise process of substrates being effected.
As means for solving these problems, a multilayer resist system, in particular, a three-layer resist process is attracting public attention.
The three-layer resist process includes the following processes:    (a) forming a lower resist layer comprising an organic material on a substrate,    (b) laminating on the lower resist layer an intermediate layer and an upper resist layer comprising an organic material crosslinkable or decomposable upon irradiation with radiation, and    (c) forming a prescribed pattern on the upper resist layer, and then etching the intermediate layer, the lower layer and the substrate successively.
As the intermediate layer used here, organopolysiloxane (a silicone resin) and an SiO2 coating solution (SOG) are so far been known.
An intermediate layer is a layer having a function of transferring the pattern of an upper layer to a lower layer by etching process and is provided between an upper layer resist and a lower layer resist. Thus, a lower layer pattern having a high aspect ratio transferred to the lower layer mainly by dry etching with the intermediate layer as the mask can be obtained
With respect to intermediate layers, various materials are reported, e.g., improved organopolysiloxane materials are disclosed in JP-B-4-43264 (the term “JP-B” as used herein means an “examined Japanese patent publication”), intermediate layers using silicone compounds, e.g., Si(OH)4,are disclosed in JP-B-6-38400, the materials of intermediate layers comprising silylated products of clay minerals are disclosed in Japanese Patent 2573371, the materials of intermediate layers comprising the mixtures of halogenosilane or organohalogenosilane and ammonia or amines are disclosed in Japanese Patent 2641644, the materials of intermediate layers comprising polysiloxane derivatives are disclosed in Japanese Patent 2901044, and the materials of intermediate layers comprising organopolysilsesquioxane are disclosed in JP-B-4-44741.
However, these intermediate layers are substantially inferior in preservation stability, and have critical defects, e.g., the upper layer resist pattern formed on an intermediate layer becomes a trapezoidal form and deteriorates line roughness edge (LER) in etching the intermediate layer with the upper layer resist pattern as the mask. In addition, they have a defect of bringing about pattern peeling of the upper layer. Moreover, the etching rate of intermediate layers is not sufficient.